Presently, the increasing trend of the use of integrated circuitry in portable and other battery powered devices increases the need for power consumption reduction in advanced integrated circuits. Some power reduction can be achieved by reducing power to portions of a circuit when they are inactive. The consumption of dynamic power by clocked circuitry can be reduced, for example, by gating the clock to portions of an integrated circuit, for example an ASIC or SOC that has multiple design blocks, by gating or halting a clock to that portion. However, even when the switching power due to the action of the clock signal is not consumed, static power loss due to leakage current and standby current will still occur. The use of power gating to remove the power supply to portions of an ASIC or SOC is therefore increasing, as a method to further reduce power consumption by inactive circuitry.
FIG. 1 depicts a block diagram of an integrated circuit 11, which may be for example an ASIC, or SOC, comprising design blocks V1, V2 and V3. Several approaches known in the prior art for gating power to certain blocks are depicted in FIG. 1. For example, power switch 13, which may be internally or externally controlled, gates power to a design block V3. A switchable power pad 15 controls the supply of power to another design block V2. An off chip power regulator implemented as a switchable voltage regulator 19 is shown, depicting another known approach.
FIG. 2 depicts in a simple circuit diagram an on-chip power gating circuit for an ARM circuit function of the prior art. A fixed supply VDD_SOC, for example 1.2 Volts, is provided on a conductor. A second supply VDD_CORE, which may the same or somewhat lower than VDD_SOC, is provided on a second conductor. Some portions of the circuitry are coupled in a fixed voltage manner to one or the other of these power supply conductors, for example RAM 31 is coupled to voltage supply VDD_CORE. A CPU SOC 35 is similarly coupled to the higher voltage supply VDD_SOC. A third circuit portion, CORE 33, has a dynamic voltage supply (DVS) which is turned on and off based on some periods of circuit inactivity. This phenomenon is often referred to as a “sleep” cycle. PMOS transistors 37 are shown coupled in a serial fashion to a control signal labeled “Sleep”. When the PMOS transistors are cut off, (Sleep is a logical high value, as PMOS transistors 37 are turned on when the gate terminal falls below VDD), that is −Vgs is greater than a threshold voltage, the power supplied to the CORE 33 is gated off. When the Sleep control line falls, for example to a logical zero value, the CPRE 33 circuitry receives a voltage supply input.
As shown in FIG. 2, the PMOS transistors are serially coupled and when the last transistor 37 receives the Sleep signal, acknowledge signal (ACK) indicates all of the transistors are active, or, inactive. In this manner the system can monitor when all of the VDD_CORE_VDDV portions are coupled to VDD_CORE.
Prior art power gating circuits may implement a sequence for powering up blocks. In FIG. 3, for example, the VDD supply is coupled to a grid of conductors 21 that provide a VDD voltage to a plurality of locations, perhaps in an ASIC or SOC device. For example in a multiple level metal semiconductor device, power rails 21 may be comprised of copper or aluminum metallization and may be routed as a grid of conductors across the device. The gating PMOS transistors 25 in FIG. 3 provide a gated supply voltage VDD_G to a second group of conductors 23, which then supply power to the gated circuit blocks 29.
In FIG. 3, dashed line 27 indicates a sequence for turning on the PMOS gating transistors to control the power up sequence. This is done to control the current as the circuitry is powered on.
The power on process has a peak current during the time the gated power supply conductors are being raised to VDD. Once that voltage is established across the device, current flowing drops. The more current that is allowed to flow at once, the faster the ramp up time from 0V or a discharged state to VDD, or a charged state, will be. FIG. 4 depicts an exemplary current vs. voltage graph for the current Ids flowing through a PMOS “header” transistor that is coupled between a VDD supply and a gated VDD supply and provides the power to a portion of a gated power supply circuit. At time “1” in the diagram, the transistor is cut off and no current flows. As the gate voltage falls below VDD (turning on the PMOS as the voltage Vgs falls) the transistor turns on and is in saturation at time 2, in other words further decreases in the gate voltage do not provide additional current flow. As the current being supplied from the VDD supply to the gated VDD line falls, as the VDD line rises towards the higher rail, the transistor current falls and the transistor is now in a steady state situation in the linear, or resistive region with a smaller current, nearly zero, flowing through it. (Vds is small as the drain rises to nearly the source voltage).
FIG. 5 depicts three curves for the ramp up time of a VDD gated voltage supply using three different approaches. In a “fish bone” approach where multiple PMOS transistors are turned on to simultaneously couple all of the portions of the circuit supplied by the gated voltage at once, as shown in the solid line, the current peaks very early but the VDD voltage from the gating circuitry reaches the VDD level fairly early. Thus the concurrence approach has a short ramp-up time. An alternative approach, as represented by the line with dashes interspersed with a single dot and labeled “mutation (domino)”, the transistors are turned on in groups in a domino fashion, and the current reaches smaller peak value, however the VDD ramp up time is longer. Finally, in the third approach, represented in the graphs by the line that is dashes interspersed with two dots between them, labeled “one by one (daisy chain)”, the current peaks at a smaller value; as each portion of the gated circuit is coupled to the supply voltage one at a time in serial fashion, however the VDD ramp up time is the longest. The graphs of voltage and current in the figure illustrate a design trade-off between current and ramp up time. The more current that is allowed to flow at the peak, the faster the gated VDD voltage will ramp up to VDD.
A problem with the power switches and routing fabric of the prior art, for example for the design of ASIC or SOC devices, is the power fabric and switch placement and topology is typically fixed. For some designs implemented using the switch placement and routing fabric will have characteristics that make the power on process work well. However, if the same power switch placement and routing topology is used for another device implemented in the same design flow, the placement and power on sequence used may not be optimal for that second device. For example in FIG. 6. device A has a good fit to the power switch fabric, while for the device labeled B, the power switch fabric is not suitable,
Thus, there is a continuing need for improved methods and structures to address these and other problems with the power switch cells and routing of the prior art as used in advanced semiconductor processes to implement SOCs.